Many electrical circuits are composed of multiple functional units, in which the supply voltage of each functional unit is adjusted in order to minimize the overall system-level power consumption. To interface between those blocks, a voltage level shifter is employed to switch between the voltage levels of the respective functional blocks. Although level shifters can shift from low to high voltage or from high to low voltage, the following discussion focuses on the former type.
It should be appreciated that the terms "low voltage" and "high voltage" are used herein in their relative senses without limiting them to actual values, that is, "low" is simply low relative to "high." For example, a "low" voltage may have a voltage level at logic low of less than 0.7 V and a voltage level at logic high of 2.5V while a "high" voltage may have a voltage level at logic 0 of less than 1.0V and a voltage level at logic high of greater than 5V. Other values are certainly contemplated and are within the general scope of the present invention.
In order to simplify the system layout, a level shifter can be thought of as divided into two parts: a sender and a receiver. The sender is the input section of the level shifter and works at low voltage and the receiver is the output section and works at high voltage. In this way, suppose a block A works with low voltage, and a block B works with high voltage. The layout or block A would include the sender portion of a level shifter and the layout or block B would include the receiver portion of the level shifter.
FIG. 1 shows a well known circuit implementation of a voltage level shifter 10. The level shifter 10 includes an input terminal 11 that receives a low voltage input signal INP and an input inverter 12 that inverts the input signal to produce a complementary input signal INP_INV. Respectively connected to the input terminal 11 and the output of the input inverter 12 are gate terminals of first and second NMOS transistors MN1, MN2, both of which have source terminals coupled to ground. The second NMOS transistor also has a drain terminal that acts as an output terminal 13. Respectively connected in series to drain terminals of the first and second NMOS transistors MN1, NN2 are drain terminals of cross-coupled first and second PMOS transistors MP1, MP2, both of which have source terminals coupled to a high voltage supply reference. The first and second PMOS transistors are cross-coupled in that a gate terminal of the first PMOS transistor MP1 is coupled to the drain terminal of the second PMOS transistor MP2, which has a gate terminal coupled to the drain terminal of the first PMOS transistor MP1. The first and second NMOS and PMOS transistors MN1, MN2, MP1, MP2 together comprise a level shifting stage 14. The capacitances C1, C2 shown in FIG. 1 are wire capacitances of the line connecting the input node to the first NMOS transistor MN1 and the line connecting the input inverter 12 to the second NMOS transistor MN2, respectively.
The level shifter 10 converts the low voltage input signal INP at the input node 11 to a high voltage output signal OUT at the output node 13 as follows. When the input signal is logic low, the first NMOS transistor MN1 is "off" and the second NMOS transistor MN2 is "on" via the input inverter 12. As a result, the second NMOS transistor electrically connects the output node 13 to ground which drives the output signal OUT to logic low. Further, the logic low output signal OUT turns "on" the first PMOS transistor which provides the high voltage supply reference to the gate terminal of the second PMOS transistor, which thereby is held "off."
When the input signal INP goes high, the first NMOS transistor MN1 is turned "on" and the second NMOS transistor MN2 is turned "off." Turning "on" the first NMOS transistor electrically connects to ground the gate terminal of the second PMOS transistor MP2, which thereby is turned "on" and provides the high voltage supply reference to the output node 13.
It will be appreciated that the first NMOS transistor MN1 will turn "on" before the second NMOS transistor MN2 will turn "off" because of the delay introduced by the input inverter 12. This causes a short circuit current to flow between the high voltage supply reference and ground via the NMOS and PMOS transistors MN1, MP1. Because the first NMOS transistor MN1 is stronger than the first PMOS transistor MP1, the second PMOS transistor MP2 will be switched "on", causing a second short current to flow via the second NMOS and PMOS transistors MN2, MP2. These short circuit currents flow until the second NMOS transistor MN2 is turned "off" by the input inverter 12, which allows the second PMOS transistor MP2 to turn "off" the first PMOS transistor MP1.
The mismatch in arrival times of the input signal INP and its complement INP_INV to the NMOS transistors MN1, MN2 can be exacerbated by large wire capacitances C1, C2 and by differences in the wire capacitances C1, C2. Such differences in the wire capacitances C1, C2 can occur if the lines to the NMOS transistors MN1, MN2 are wired differently. Such wire capacitances C1, C2 typically do differ considerably because the sender and receiver portions of the level shifter typically are implemented in separate low voltage and high voltage wells of a semiconductor substrate. The bigger the capacitance values C1, C2, or their mismatch, or the eventual crosstalk effect, the longer the short circuit currents flow and more power is consumed. The added short circuit currents caused by the capacitive differences wastes energy and can cause serious power dissipation problems.